As electronic industry evolves rapidly, electronic products having small form factors are desired. Better performance, better functionality and higher speed are of interest. In order to meet requirements such as high integration and miniaturization of the semiconductor devices, circuit boards that provide a plurality of active/passive components and circuits have evolved from double layers to multi-layers, in order to expand the available circuit layouts on the circuit boards through interlayer connection under confined spaces.
In the industry of carrier board manufacturing, low cost, high reliability and high routing density have always been the objectives. In order to achieve these objectives, a technique called “build up” technique has been developed, which essentially stacks a plurality of dielectric layers and circuit layers on one another and forms conductive structures such as blind vias or plated through holes for electrically connecting the various circuit layers.
In addition, along with the rapid growth of various portable devices, packaging techniques such as BGA, flip-chip, CSP (chip-size packaging) and MCM (multi-chip module) and even carrier structures embedded with semiconductor elements are becoming the mainstream of the semiconductor market.
Referring now to FIG. 1A, U.S. Pat. No. 6,154,366 titled “Structures and Processes for Fabricating Moisture Resistant Chip-on-Flex Packages” is illustrated. As shown, a lower surface 10a of the flex component 10 is attached to a microelectronic die 11 having an active surface 11a with contacts 111. An encapsulating material 12 is formed on the lower surface 10a of the flex component 11 and the exposed surfaces of the microelectronic die 11. A conductive circuit layer 13 is formed on the flex component 10. Blind vias 131 is formed in the flex component 13 to electrically connect the contacts 11 of the microelectronic die 11. Similar elements may be used to form additional circuit build up structures 14. A moisture barrier 15 is formed on the top surface of the circuit build up structure 14, the side surfaces of the circuit build up structure 14 and the encapsulating material 12 and the bottom surface of the encapsulating material 12 to prevent the circuit layers 13 in the circuit build up structure 14 from moisture.
The moisture barrier 15 may include: sol-gel oxides (e.g. tungsten oxide) formed by the sol-gel technique; PCTFE (polychloro-trifluoro-ethylene) or high-density organic coatings (e.g. photoresist) formed by coating; and metal oxides formed by metal deposition followed by thermal oxidation. Considering the effect of oxidation, which has a thickness from 0.1 to 1μ, the material is preferably titanium having a fully oxidized temperature of 200° C.
Although the moisture barrier 15 in this case fully covers the encapsulating material 12 and the circuit build up structure 14, but the morphology of the moisture barrier formed by sol-gel or coating is rather loose, as a result, moisture may still permeate into the various structural layers. Whereas the moisture barrier 15 formed using thermal oxidation is not only process-complicated but the materials available for selection as well as its thickness are rather limited.
Referring to FIG. 1B, a complete final product of an alternative of the aforementioned structure is shown, wherein a first moisture barrier 15a is formed on the top surface of the circuit build up structure 14, and a second moisture barrier 15b is formed on the bottom surface of the encapsulating material 12. First and second solder mask layers 16a and 16b are formed on the first and second moisture barriers 15a and 15b respectively. Deep vias 156 are formed in the first moisture barrier 15a and the first solder mask layer 16a to expose the electrically connecting pads in the circuit build up structure 14, so as to form conductive structures 17 in the deep vias 156.
The first and second moisture barriers 15a and 15b are only formed on the top surface of the circuit build up structure 14 and the bottom surface of the encapsulating material 12, the side surfaces of the encapsulating material 12 and the circuit build up structure 14 are not protected. As a result, moisture, oil and contaminations may easily enter between the encapsulating material 12 and the circuit build up structure 14 and travel to the junction of the various circuits in the circuit build up structure 14, causing delamination or even oxidation or erosion of the circuits.
Furthermore, since the microelectronic die 11 is embedded into the encapsulating material 12, the electrical performance of the microelectronic die 11 completely rely on the circuit layer 13 on the top surface of the flex component 10 and the build up structure 14, and hence are limited. Moreover, the encapsulating material 12 occupies precious space but has no electrical performance at all.
In addition, the microelectronic die 11 is completely embedded in the encapsulating material 12 and covered by the flex component 10, the circuit layer 13 and the circuit build up structure 14, heat cannot be easily dissipated outside, which may cause deleterious effect during high-speed operations.
Therefore, there is a need to provide a chip carrier structure to prevent moisture from intruding into the chip carrier structure and causing delamination as is the case in the prior art, as well as to improve heat dissipation and space utilization.